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| LMV331, LMV393, LMV339 Single, Dual, Quad General Purpose, Low Voltage Comparators The LMV331 is a CMOS single channel, general purpose, low voltage comparator. The LMV393 and LMV339 are dual and quad channel versions, respectively. The LMV331/393/339 are specified for 2.7 V to 5 V performance, have excellent input common-mode range, low quiescent current, and are available in several space saving packages. The LMV331 is available in a 5-pin SC-70, a TSOP-5, and a ULLGA8 package. The LMV393 is available in a 8-pin Micro8t, SOIC-8, and a UDFN8 package, and the LMV339 is available in a SOIC-14 and a TSSOP-14 package. The LMV331/393/339 are cost effective solutions for applications where space saving, low voltage operation, and low power are the primary specifications in circuit design for portable applications. Features http://onsemi.com 1 5 1 TSOP-5 CASE 483 SC-70 CASE 419A 1 ULLGA8 CASE 613AG 1 * * * * * * * * * * * Guaranteed 2.7 V and 5 V Performance Input Common-mode Voltage Range Extends to Ground Open Drain Output for Wired-OR Applications Low Quiescent Current: 60 mA/channel TYP @ 5 V Low Saturation Voltage 200 mV TYP @ 5 V Propagation Delay 200 ns TYP @ 5 V These are Pb-Free Devices Battery Monitors Notebooks and PDA's General Purpose Portable Devices General Purpose Low Voltage Applications +VCC Micro8 CASE 846A 8 8 1 SOIC-8 CASE 751 1 UDFN8 CASE 517AJ Typical Applications 1 SOIC-14 CASE 751A 1 TSSOP-14 CASE 948G ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. R1 VIN - RPULL-UP VO VCC VO VT2 VT1 VIN V+ + RLOAD 0 R3 R2 Figure 2. Hysteresis Curve Figure 1. Inverting Comparator with Hysteresis (c) Semiconductor Components Industries, LLC, 2009 October, 2009 - Rev. 3 1 Publication Order Number: LMV331/D LMV331, LMV393, LMV339 MARKING DIAGRAMS SC-70 CASE 419A 5 CCAMG G 1 CCA = Specific Device Code M = Date Code G = Pb-Free Package (Note: Microdot may be in either location) Micro8 CASE 846A 8 V393 AYWG G 1 A = Assembly Location Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) SOIC-14 CASE 751A 14 LMV339 AWLYWWG 1 A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package A L Y W G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 14 LMV 339 ALYWG G A L Y W G 3CAAYWG G CAMG G TSOP-5 CASE 483 UDFN8 CASE 517AJ CA = Specific Device Code A = Assembly Location M = Date Code Y = Year G = Pb-Free Package W = Work Week (Note: Microdot may be in either location) G = Pb-Free Package (Note: Microdot may be in either location) SOIC-8 CASE 751 8 V393 ALYW G G ULLGA8 CASE 613AG 1 XXMG 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package XX = Specific Device Code M = Date Code G = Pb-Free Package TSSOP-14 CASE 948G (Note: Microdot may be in either location) PACKAGE PINOUTS SC-70/TSOP-5 +IN GND -IN 1 2 3 5 Micro8 / SOIC-8 / UDFN8 VCC Output A 1 2 8 7 6 5 SOIC-14 / TSSOP-14 Output 2 Output 1 VCC - Input 1 + Input 1 - Input 2 1 2 3 4 5 6 7 14 13 12 VCC Output B Inputs B Output 3 Output 4 GND + Input 4 - Input 4 + Input 3 - Input 3 + - 4 OUTPUT Inputs A GND 3 4 - + - + (Top Views) IN- IN+ VCC-/GND 1 ULLGA8 NC 8 7 (Top Views) OUT NC VCC+ NC - No Internal Connection * 1 ) *2 ) 4 ) * ) * 11 10 9 8 2 6 3 + Input 2 3 4 5 (Top Views) NC (Top Views) http://onsemi.com 2 LMV331, LMV393, LMV339 MAXIMUM RATINGS Symbol VS VIDR TJ Tstg TL VESD Voltage on any Pin (referred to V- pin) Input Differential Voltage Range Maximum Junction Temperature Storage Temperature Range Mounting Temperature (Infrared or Convection (1/16 From Case for 30 Seconds)) ESD Tolerance (Note 1) Machine Model Human Body Model Rating Value 5.5 Supply Voltage 150 -65 to 150 260 100 1000 Unit V V C C C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol VCC qJA Parameter Supply Voltage Temperature Range (Note 2) Thermal Resistance SC-70 TSOP-5 ULLGA8 Micro8 SOIC-8 UDFN8 SOIC-14 TSSOP-14 Value 2.7 to 5.0 280 333 340 238 212 350 156 190 Unit V C/W 1. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). 2. The maximum power dissipation is a function of TJ(MAX), qJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/qJA. All numbers apply for packages soldered directly onto a PC board. http://onsemi.com 3 LMV331, LMV393, LMV339 2.7 V DC ELECTRICAL CHARACTERISTICS (All limits are guaranteed for TA = 25C, V+ = 2.7 V, V- = 0 V, VCM = 1.35 V unless otherwise noted.) Parameter Input Offset Voltage Input Offset Voltage Average Drift Input Bias Current (Note 3) Input Offset Current (Note 3) Input Voltage Range Saturation Voltage Output Sink Current Supply Current LMV331 LMV393 LMV339 Symbol VIO TC VIO IB IIO VCM VSAT IO ICC ISINK 1 mA VO 1.5 V 5 Condition Min Typ 1.7 5 <1 <1 0 to 2 120 23 40 70 140 100 140 200 Max 9 Unit mV mV/C nA nA V mV mA mA 2.7 V AC ELECTRICAL CHARACTERISTICS (TA = 25C, V+ = 2.7 V, RL = 5.1 kW, V- = 0 V unless otherwise noted.) Parameter Propagation Delay - High to Low Propagation Delay - Low to High Symbol tPHL tPLH Condition Input Overdrive = 10 mV Input Overdrive = 100 mV Input Overdrive = 10 mV Input Overdrive = 100 mV Min Typ 1000 500 800 200 Max Unit ns ns 3. Guaranteed by design and/or characterization. http://onsemi.com 4 LMV331, LMV393, LMV339 otherwise noted.) 5.0 V DC ELECTRICAL CHARACTERISTICS (All limits are guaranteed for TA = 25C, V+ = 5 V, V- = 0 V, VCM = 2.5 V unless Parameter Input Offset Voltage Input Offset Voltage Average Drift Input Bias Current (Note 4) Input Offset Current (Note 4) Input Voltage Range Voltage Gain (Note 4) Saturation Voltage Output Sink Current Supply Current Supply Current Supply Current LMV331 LMV393 LMV339 IB IIO VCM AV VSAT IO ICC ICC ICC ISINK 4 mA TA = -40C to +85C VO 1.5 V TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C V+ = 5 V, RL = 5.1 kW, V- 10 20 Symbol VIO Condition TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C Min Typ 1.7 5 <1 <1 0 to 4.2 50 200 84 60 100 170 0.003 120 150 200 250 300 350 1 400 700 Max 9 Unit mV mV/C nA nA V V/mV mV mA mA mA mA mA Output Leakage Current (Note 4) 5.0 V AC ELECTRICAL CHARACTERISTICS (TA = 25C, Parameter Propagation Delay - High to Low Propagation Delay - Low to High Symbol tPHL tPLH = 0 V unless otherwise noted.) Typ 1500 900 800 200 Max Unit ns ns Condition Input Overdrive = 10 mV Input Overdrive = 100 mV Input Overdrive = 10 mV Input Overdrive = 100 mV Min 4. Guaranteed by design and/or characterization. http://onsemi.com 5 LMV331, LMV393, LMV339 TYPICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C, RL = 5 kW unless otherwise specified) 50 45 SUPPLY CURRENT (mA) 40 35 30 25 20 15 10 5 0 0 1 85C -40C 25C SUPPLY CURRENT (mA) 30 -40C 25C 85C 20 10 2 3 SUPPLY VOLTAGE (V) 4 5 0 0 1 2 3 SUPPLY VOLTAGE (V) 4 5 Figure 3. LMV331Supply Current vs. Supply Voltage (Output High) 180 160 140 120 VSAT (mV) 100 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 10 85C 25C VSAT (mV) -40C 600 500 400 300 200 100 0 0 Figure 4. LMV331Supply Current vs. Supply Voltage (Output Low) 85C 25C -40C 10 OUTPUT CURRENT (mA) 20 30 OUTPUT CURRENT (mA) 40 50 Figure 5. VSAT vs. Output Current at VCC = 2.7 V Figure 6. VSAT vs. Output Current at VCC = 5.0 V http://onsemi.com 6 LMV331, LMV393, LMV339 NEGATIVE TRANSITION INPUT - VCC = 2.7 V Timebase 5.00 kS -600 500 ns/div 1.0 GS/s Trigger Stop Edge 28 mV Negative Figure 7. 10 mV Overdrive Timebase 2.00 kS -200 200 ns/div 1.0 GS/s Trigger Stop Edge 11.5 mV Negative Figure 8. 20 mV Overdrive Timebase 5.00 kS -600 500 ns/div 1.0 GS/s Trigger Stop Edge 18 mV Negative Figure 9. 100 mV Overdrive http://onsemi.com 7 LMV331, LMV393, LMV339 POSITIVE TRANSITION INPUT - VCC = 2.7 V Timebase 2.00 kS -400 200 ns/div 1.0 GS/s Trigger Stop Edge =11.5 mV Positive Figure 10. 10 mV Overdrive Timebase 1.00 kS -300 100 ns/div 1.0 GS/s Trigger Stop Edge -49.5 mV Positive Figure 11. 20 mV Overdrive Timebase 1.00 kS -150 100 ns/div 1.0 GS/s Trigger Stop Edge 18 mV Positive Figure 12. 100 mV Overdrive http://onsemi.com 8 LMV331, LMV393, LMV339 NEGATIVE TRANSITION INPUT - VCC = 5.0 V Timebase 5.00 kS -600 500 ns/div 1.0 GS/s Trigger Stop Edge 28 mV Negative Figure 13. 10 mV Overdrive Timebase 2.00 kS -200 200 ns/div 1.0 GS/s Trigger Stop Edge 11.5 mV Negative Figure 14. 20 mV Overdrive Timebase 5.00 kS -600 500 ns/div 1.0 GS/s Trigger Stop Edge 18 mV Negative Figure 15. 100 mV Overdrive http://onsemi.com 9 LMV331, LMV393, LMV339 POSITIVE TRANSITION INPUT - VCC = 5.0 V Timebase 2.00 kS -400 200 ns/div 1.0 GS/s Trigger Stop Edge -11.5 mV Positive Figure 16. 10 mV Overdrive Timebase 1.00 kS -300 100 ns/div 1.0 GS/s Trigger Stop Edge -49.5 mV Positive Figure 17. 20 mV Overdrive Timebase 1.00 kS -150 100 ns/div 1.0 GS/s Trigger Stop Edge 18 mV Positive Figure 18. 100 mV Overdrive http://onsemi.com 10 LMV331, LMV393, LMV339 APPLICATION CIRCUITS Basic Comparator Operation The basic operation of a comparator is to compare two input voltage signals, and produce a digital output signal by determining which input signal is higher. If the voltage on the non-inverting input is higher, then the internal output transistor is off and the output will be high. If the voltage on the inverting input is higher, then the output transistor will be on and the output will be low. The LMV331/393/339 has an open-drain output stage, so a pull-up resistor to a positive supply voltage is required for the output to switch properly. The size of the pull-up resistor is recommended to be between 1 kW and 10 kW. This range of values will balance two key factors; i.e., power dissipation and drive capability for interface circuitry. Figure 19 illustrates the basic operation of a comparator and assumes dual supplies. The comparator compares the input voltage (VIN) on the non-inverting input to the reference voltage (VREF) on the inverting input. If VIN is less than VREF, the output voltage (VO) will be low. If VIN is greater than VREF, then VO will be high. VOUT V+ +VCC R1 VIN - RPULL-UP VO V+ + RLOAD R3 R2 Figure 20. Inverting Comparator with Hysteresis VREF 0V VIN V+ +VIN + Time When VIN is less than the voltage at the non-inverting node, V+, the output voltage will be high. When VIN is greater than the voltage at V+, then the output will be low. The hysteresis band (Figure 21) created from the resistor network is defined as: DV ) + V T1 * V T2 where VT1 and VT2 are the lower and upper trip points, respectively. VCC 3.0 k VO +VREF - VO VT2 0 VIN VT1 Figure 19. Comparators and Stability Figure 21. A common problem with comparators is oscillation due to their high gain. The basic comparator configuration in Figure 19 may oscillate if the differential voltage between the input pins is close to the device's offset voltage. This can happen if the input signal is moving slowly through the comparator's switching threshold or if unused channels are connected to the same potential for termination of unused channels. One way to eliminate output oscillations or `chatter' is to include external hysteresis in the circuit design. Inverting Configuration with Hysteresis VT1 is calculated by assuming that the output of the comparator is pulled up to supply when high. The resistances R1 and R3 can be viewed as being in parallel which is in series with R2 (Figure 22). Therefore VT1 is: V T1 + V CC R 2 R1 o R3 ) R2 VT2 is calculated by assuming that the output of the comparator is at ground potential when low. The resistances R2 and R3 can be viewed as being in parallel which is in series with R1 (Figure 23). Therefore VT2 is: V T2 + V CC R 2 o R 3 R1 ) R2 o R3 An inverting comparator with hysteresis is shown in Figure 20. http://onsemi.com 11 LMV331, LMV393, LMV339 VO HIGH +VCC VO LOW +VCC R1 R1 VT1 R2 R3 VT2 R2 R3 When VIN is much less than the voltage at the inverting input (VREF), then the output is low. R2 can then be viewed as being connected to ground (Figure 26). To calculate the voltage required at VIN to trip the comparator high, the following equation is used: V in1 + V ref (R 1 ) R 2) R2 When the output is high, VIN must less than or equal to VREF (VIN VREF) before the output will be low again (Figure 27). The following equation is used to calculate the voltage at VIN to switch the output back to the low state: V in2 + V ref (R 1 ) R 2) * V CCR 1 R2 VO HIGH +VCC Figure 22. Figure 23. Non-inverting Configuration with Hysteresis A non-inverting comparator is shown in Figure 24. +VCC VO LOW VIN1 R1 VA = VREF R2 VA = VREF R1 VREF - RPULL-UP VO R2 VIN2 VIN R1 R2 VA + RLOAD Figure 26. Termination of Unused Inputs Figure 27. Figure 24. The hysteresis band (Figure 25) of the non-inverting configuration is defined as follows: DV in + V CCR 1 R 2 VCC Proper termination of unused inputs is a good practice to keep the output from `chattering.' For example, if one channel of a dual or quad package is not being used, then the inputs must be connected to a defined state. The recommended connections would be to tie one input to VCC and the other input to ground. VO VIN2 0 VIN VIN1 Figure 25. http://onsemi.com 12 LMV331, LMV393, LMV339 ORDERING INFORMATION Order Number LMV331SQ3T2G LMV331SN3T1G LMV331MU3TBG* LMV393DMR2G LMV393DR2G LMV393MUTAG LMV339DR2G LMV339DTBR2G Number of Channels Single Single Single Dual Dual Dual Quad Quad Specific Device Marking CCA 3CA 3C V393 V393 CA LMV339 LMV 339 Package Type SC-70 (Pb-Free) TSOP-5 (Pb-Free) ULLGA8 (Pb-Free) Micro8 (Pb-Free) SOIC-8 (Pb-Free) UDFN8 (Pb-Free) SOIC-14 (Pb-Free) TSSOP-14 (Pb-Free) Shipping 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel 4000 / Tape & Reel 2500 / Tape & Reel 3000 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Contact factory. http://onsemi.com 13 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS SC-88A, SOT-353, SC-70 CASE 419A-02 ISSUE J G A 5 4 S 1 2 3 -B- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A-01 OBSOLETE. NEW STANDARD 419A-02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 D 5 PL 0.2 (0.008) M B M N J C DIM A B C D G H J K N S H K http://onsemi.com 14 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS TSOP-5 CASE 483-02 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 NOTE 5 2X D 5X 0.20 C A B M 0.10 T 0.20 T L A 5 1 2 4 3 2X B S K DETAIL Z G DETAIL Z C 0.05 H T SEATING PLANE J SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 mm inches SCALE 10:1 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS UDFN8 1.8x1.2, 0.4P CASE 517AJ-01 ISSUE O D 0.10 C PIN ONE REFERENCE AB L1 DETAIL A NOTE 5 E 0.10 C TOP VIEW (A3) A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH MAY NOT EXCEED 0.03 ONTO BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. DIM A A1 A3 b b2 D E e L L1 L2 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 0.30 REF 1.80 BSC 1.20 BSC 0.40 BSC 0.45 0.55 0.00 0.03 0.40 REF 0.05 C 0.05 C (b2) (L2) 8 5 8X b EEE EEE e/2 1 SIDE VIEW A1 C SEATING PLANE e 4 DETAIL A 8X L MOUNTING FOOTPRINT* SOLDERMASK DEFINED 0.10 0.05 M M BOTTOM VIEW CAB C NOTE 3 0.22 7X 0.66 8X 1.50 1 0.32 0.40 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 16 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS Micro8t CASE 846A-02 ISSUE H D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. MILLIMETERS NOM MAX -- 1.10 0.08 0.15 0.33 0.40 0.18 0.23 3.00 3.10 3.00 3.10 0.65 BSC 0.40 0.55 0.70 4.75 4.90 5.05 MIN -- 0.05 0.25 0.13 2.90 2.90 INCHES NOM -- 0.003 0.013 0.007 0.118 0.118 0.026 BSC 0.016 0.021 0.187 0.193 MIN -- 0.002 0.010 0.005 0.114 0.114 HE E PIN 1 ID e b 8 PL 0.08 (0.003) M TB S A S -T- PLANE 0.038 (0.0015) A1 SEATING A c L DIM A A1 b c D E e L HE MAX 0.043 0.006 0.016 0.009 0.122 0.122 0.028 0.199 SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 8X 3.20 0.126 4.24 0.167 5.28 0.208 6X 0.65 0.0256 SCALE 8:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AJ -X- A 8 5 B 1 S 4 0.25 (0.010) M Y M -Y- G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C -Z- H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 18 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS ULLGA8, 1.5x1.5, 0.5P CASE 613AG-01 ISSUE O D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. DIM A A1 b b1 D E e L L1 L3 MILLIMETERS MIN MAX --- 0.40 0.00 0.05 0.20 0.30 0.30 0.40 1.50 BSC 1.50 BSC 0.50 BSC 0.25 0.35 0.05 REF 0.15 REF 0.10 C 0.10 C 0.05 C 8X 0.05 C SIDE VIEW b1 1 3 L3 1 0.42 8X L1 BOTTOM VIEW EEE EEE EEE 7 PIN ONE REFERENCE E TOP VIEW A SEATING PLANE A1 C MOUNTING FOOTPRINT* 7X 0.32 0.51 8X e 8X L PACKAGE OUTLINE 1.65 5 0.50 PITCH DIMENSIONS: MILLIMETERS b 0.10 C A B 0.05 C NOTE 3 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 19 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS SOIC-14 CASE 751A-03 ISSUE H -A- 14 8 -B- P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C -T- SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 20 LMV331, LMV393, LMV339 PACKAGE DIMENSIONS TSSOP-14 CASE 948G-01 ISSUE B M 14X K REF 0.10 (0.004) 0.15 (0.006) T U S TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ S SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT 7.06 1 0.36 14X 14X 1.26 Micro8 is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 21 EEE CCC EEE CCC A -V- 0.65 PITCH DIMENSIONS: MILLIMETERS LMV331/D |
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